// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : harness.v
// Author        : 
// Created On    : 
// Last Modified : 2022-11-16 11:28 by gaojiaming
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------


`ifndef __HARNESS_SV__
`define __HARNESS_SV__

import uvm_pkg::*;

`timescale 1ns/1ps

module harness;

//-------------------------------------{{{clk/rst_n gen

logic clk;
logic rst_n;

initial begin
   clk = 0;
   forever begin
      #500ps clk = ~clk;
   end
end

initial begin
   rst_n = 1'b0;
   #100ns;
   rst_n = 1'b1;
end

//}}}

//-------------------------------------{{{test name
initial begin
   run_test("sanity_case");
end
//}}}

//-------------------------------------{{{interface
spt_interface u_tx_if(clk, rst_n);
spt_interface u_rx_if(clk, rst_n);
cpu_interface u_reg_if(clk, rst_n);

initial begin
   uvm_config_db#(virtual spt_interface)::set(null, "uvm_test_top.env.tx_agt", "vif", u_tx_if);
   uvm_config_db#(virtual spt_interface)::set(null, "uvm_test_top.env.rx_agt", "vif", u_rx_if);
   uvm_config_db#(virtual cpu_interface)::set(null, "uvm_test_top.cpu_mst",  "vif", u_reg_if);
end
//}}}

//-------------------------------------{{{signal declare
logic  scan_en;
logic  test_mode;
logic  CPU_CS_N;
logic  CPU_RD_N;
logic  CPU_WE_N;
logic [15:0] CPU_ADDR;
logic [31:0]CPU_WDATA;
logic [31:0]CPU_RDATA;
logic  CPU_RDY_N;
logic  vid_in;
logic [15:0] data_in;
logic  vid_out;
logic [15:0] data_out;
//-------------------------------------}}}

//-------------------------------------{{{rtl inst
ppu_top u_ppu_top(
    .rst_n(rst_n),
    .clk_100m(clk),
    .scan_en(1'b0),
    .test_mode(1'b0),
    .CPU_CS_N(CPU_CS_N),
    .CPU_RD_N(CPU_RD_N),
    .CPU_WE_N(CPU_WE_N),
    .CPU_ADDR(CPU_ADDR),
    .CPU_WDATA(CPU_WDATA),
    .CPU_RDATA(CPU_RDATA),
    .CPU_RDY_N(CPU_RDY_N),
    .vid_in(vid_in),
    .data_in(data_in),
    .vid_out(vid_out),
    .data_out(data_out)
);
//-------------------------------------}}}

//-------------------------------------{{{port link
assign vid_in  = u_tx_if.valid;
assign data_in = u_tx_if.data;

assign u_rx_if.valid = vid_out;
assign u_rx_if.data  = data_out;

assign CPU_CS_N  = u_reg_if.CPU_CS_N;
assign CPU_RD_N  = u_reg_if.CPU_RD_N;
assign CPU_WE_N  = u_reg_if.CPU_WE_N;
assign CPU_ADDR  = u_reg_if.CPU_ADDR;
assign CPU_WDATA = u_reg_if.CPU_WDATA;
assign u_reg_if.CPU_RDATA = CPU_RDATA;
assign u_reg_if.CPU_RDY_N = CPU_RDY_N;
//}}}

endmodule
`endif
